The present invention relates generally to electronic circuits, and, more specifically, to a system for data transfer between asynchronous clock domains of an electronic circuit.
System-on-chips (SoCs) often include multiple clock domains that operate at different clock frequencies that are asynchronous with respect to each other. Special design and interface techniques are used to transfer data between such asynchronous clock domains. An example of one such interfacing technique is a handshake protocol. In the handshake protocol, a first clock domain, e.g., a transmitter transmits a request signal to a second clock domain, e.g., a receiver, and requests the receiver to accept data available on a data bus that connects the first and second clock domains. Thereafter, the receiver asserts an acknowledge signal, signaling that it has accepted the data.
Though the handshake protocol is simple in execution, it is fraught with shortcomings. Due to the asynchronous nature of the transmitter and receiver clock domains, the handshaking protocol is prone to setup and hold time violations, thereby leading to meta-stability and unreliable data transfer. Two stage or higher stage cascaded synchronizers may be used between the transmitter and receiver clock domains to transfer the control signals to eliminate data transfer errors. However, the handshaking protocol is rendered inefficient when the synchronizers are used for data transfer between domains that operate at substantially different clock signal frequencies. For example, a host device (i.e., a central processing unit, CPU) of a register programming interface block operating at a clock signal frequency that is different from that of a slave device (i.e., a register) of the register programming interface block and performing back-to-back write operations to the same register must wait for at least two slave and two host clock cycles. If the ratio of the frequencies of the host and slave clock signals is greater than two, the overall performance of the system is degraded. Clock cycles are wasted in synchronizing the request and acknowledgement signals and the register programming interface block is stalled during a write transaction to a slower clock domain until the handshake is completed. The data bus also is stalled while waiting on a slower clock domain for back-to back register access transactions between different peripheral controllers using the data bus, which leads to unnecessary consumption of CPU clock cycles. CPU clock cycles are important in calculation-intensive SoC applications and any waste leads to a slow response, which degrades the overall performance of the SoC.
Therefore, it would be advantageous to have a system for transferring data between asynchronous clock domains that is fast and efficient, uses the CPU clock cycles effectively, and overcomes the above-mentioned limitations of conventional data transfer systems.